Adding design rule templates for JLCPCB

2019-07-19 11:37:12 -07:00
parent 3adff7a141
commit 6fdf286e5c
14 changed files with 2464 additions and 0 deletions
--- a/JLCPCB_Multilayer/JLCPCB.kicad_pcb
+++ b/JLCPCB_Multilayer/JLCPCB.kicad_pcb
@@ -0,0 +1,111 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.2-201-g3c8f901a1)")
+
+  (general
+    (thickness 1.6002)
+    (drawings 0)
+    (tracks 0)
+    (zones 0)
+    (modules 0)
+    (nets 1)
+  )
+
+  (page USLetter)
+  (title_block
+    (rev 1)
+  )
+
+  (layers
+    (0 Front signal)
+    (1 In1.Cu signal)
+    (2 In2.Cu signal)
+    (31 Back signal)
+    (34 B.Paste user hide)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user hide)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.254)
+    (user_trace_width 0.127)
+    (user_trace_width 0.254)
+    (user_trace_width 0.508)
+    (user_trace_width 0.762)
+    (trace_clearance 0.127)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.0889)
+    (via_size 0.6858)
+    (via_drill 0.3302)
+    (via_min_size 0.45)
+    (via_min_drill 0.2)
+    (user_via 0.6858 0.3302)
+    (user_via 0.889 0.381)
+    (uvia_size 0.6858)
+    (uvia_drill 0.3302)
+    (uvias_allowed no)
+    (uvia_min_size 0)
+    (uvia_min_drill 0)
+    (edge_width 0.0381)
+    (segment_width 0.254)
+    (pcb_text_width 0.3048)
+    (pcb_text_size 1.524 1.524)
+    (mod_edge_width 0.1524)
+    (mod_text_size 0.8128 0.8128)
+    (mod_text_width 0.1524)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0)
+    (solder_mask_min_width 0.1016)
+    (aux_axis_origin 0 0)
+    (visible_elements FEFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.152400)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue false)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk true)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "./gerbers"))
+  )
+
+  (net 0 "")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.127)
+    (trace_width 0.254)
+    (via_dia 0.6858)
+    (via_drill 0.3302)
+    (uvia_dia 0.6858)
+    (uvia_drill 0.3302)
+    (diff_pair_width 0.1524)
+    (diff_pair_gap 0.254)
+  )
+
+)