Add 2 and 4 Layer templates for AISLER

This commit is contained in:
Patrick Franken
2019-07-21 10:52:26 +02:00
parent e3c36eb6b8
commit 8378838a68
16 changed files with 2506 additions and 0 deletions

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(kicad_pcb (version 20171130) (host pcbnew "(5.1.2-1)-1")
(general
(thickness 1.6002)
(drawings 0)
(tracks 0)
(zones 0)
(modules 0)
(nets 1)
)
(page A4)
(title_block
(rev 1)
)
(layers
(0 Front signal)
(31 Back signal)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(user_trace_width 0.1)
(user_trace_width 0.2)
(user_trace_width 0.5)
(trace_clearance 0.25)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.1)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.45)
(via_min_drill 0.2)
(user_via 0.45 0.2)
(user_via 0.8 0.4)
(uvia_size 0.8)
(uvia_drill 0.4)
(uvias_allowed no)
(uvia_min_size 0)
(uvia_min_drill 0)
(edge_width 0.1)
(segment_width 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.1)
(mod_text_size 0.8 0.8)
(mod_text_width 0.1)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0)
(solder_mask_min_width 0.1)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.152400)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue false)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk true)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "./gerbers_for_aisler"))
)
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.25)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.8)
(uvia_drill 0.4)
(diff_pair_width 0.25)
(diff_pair_gap 0.25)
)
(net_class Min "This is the bare minimum allowed."
(clearance 0.1)
(trace_width 0.1)
(via_dia 0.45)
(via_drill 0.2)
(uvia_dia 0.45)
(uvia_drill 0.2)
(diff_pair_width 0.12)
(diff_pair_gap 0.12)
)
)