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Add Sierra Circuits Templates

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This commit is contained in:
Seth Hillbrand
2019-10-20 16:28:34 -07:00
parent de2979e368
commit 41194bafb3
89 changed files with 105963 additions and 0 deletions
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15250
Sierra 10 layer Board/Ten Layer Board.kicad_pcb Normal file
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Sierra 10 layer Board/Ten Layer Board.pro Normal file
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update=09/24/19 23:57:07
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=10
BoardThickness=1.5748
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1016
MinViaDiameter=0.4064
MinViaDrill=0.2032
MinMicroViaDiameter=0
MinMicroViaDrill=0
MinHoleToHole=0.254
TrackWidth1=0.1524
TrackWidth2=0.1016
TrackWidth3=0.127
TrackWidth4=0.1524
TrackWidth5=0.254
TrackWidth6=0.508
TrackWidth7=0.762
ViaDiameter1=0.4572
ViaDrill1=0.254
ViaDiameter2=0.4064
ViaDrill2=0.2032
ViaDiameter3=0.4572
ViaDrill3=0.254
dPairWidth1=0.1524
dPairGap1=0.1524
dPairViaGap1=0.25
SilkLineWidth=0.127
SilkTextSizeV=0.762
SilkTextSizeH=0.762
SilkTextSizeThickness=0.127
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.254
CopperTextSizeV=1.524
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.03809999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.1524
OthersTextSizeV=1.016
OthersTextSizeH=1.016
OthersTextSizeThickness=0.1524
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.1016
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=TOP
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND_1
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=SIGNAL_1
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=POWER_1
Type=1
Enabled=1
[pcbnew/Layer.In4.Cu]
Name=SIGNAL_2
Type=0
Enabled=1
[pcbnew/Layer.In5.Cu]
Name=SIGNAL_3
Type=0
Enabled=1
[pcbnew/Layer.In6.Cu]
Name=POWER_2
Type=1
Enabled=1
[pcbnew/Layer.In7.Cu]
Name=SIGNAL_4
Type=0
Enabled=1
[pcbnew/Layer.In8.Cu]
Name=GND_2
Type=1
Enabled=1
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=BOTTOM
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.4572
uViaDrill=0.254
dPairWidth=0.1524
dPairGap=0.1524
dPairViaGap=0.25

2173
Sierra 10 layer Board/Ten Layer Board.sch Normal file
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Sierra 10 layer Board/meta/ICON.png Normal file
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Sierra 10 layer Board/meta/Images/Design Rules.JPG Normal file
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Sierra 10 layer Board/meta/Images/Net Classes.JPG Normal file
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Sierra 10 layer Board/meta/Images/Solder Mask & Paste.JPG Normal file
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Sierra 10 layer Board/meta/Images/Text & Graphics.JPG Normal file
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Sierra 10 layer Board/meta/Images/Thumbs.db Normal file
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Sierra 10 layer Board/meta/Images/Trace & Vias.JPG Normal file
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Sierra 10 layer Board/meta/Images/layout.jpg Normal file
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Sierra 10 layer Board/meta/info.html Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
<title>Sierra Circuit 10 Layer </title>
</head>
<body>
<h2>Sierra Circuit - 10 Layer</h2>
<img src="icon.png" alt="Sierra Circuit"/>
<p> This Template consist of following
<br> 1. Schematic Template with 1 page, user can create more pages. It is ideal to keep block diagram in page1, schematic in rest of the pages. Final page should consist of revision history.
<br> 2. Default board (Layout) with Sierra Circuit rules for 10-layerboards, It consist of standard stackup, consumers can create custom stackup.
</p>
<br> For details visit us at https://www.protoexpress.com or CALL US (800) 763.7503
Template Information & Rules are as follows.
<br>
<br> Schematic Sample
<br> <img src="Images/schematic.jpg" alt="Schematic"/>
<br>
<br>
<br> Layout Sample
<br> <img src="Images/layout.jpg" alt="layout"/>
<br>
<br>
<br> Design Rules details
<br> <img src="Images/Layers.JPG" alt="Layers"/>
<br>
<br>
<br> <img src="Images/Text & Graphics.JPG" alt="Text & Graphics"/>
<br>
<br>
<br> <img src="Images/Design Rules.JPG" alt="Design Rules"/>
<br>
<br>
<br> <img src="Images/Net Classes.JPG" alt="Net Classes"/>
<br>
<br>
<br> <img src="Images/Trace & Vias.JPG" alt="Trace & Vias"/>
<br>
<br>
<br> <img src="Images/Solder Mask & Paste.JPG" alt="Solder Mask & Paste"/>
</body>
</html>

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Sierra 12 layer Board/Twelve Layer Board.kicad_pcb Normal file
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Sierra 12 layer Board/Twelve Layer Board.pro Normal file
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update=09/24/19 08:58:00
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=12
BoardThickness=1.5748
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1016
MinViaDiameter=0.4064
MinViaDrill=0.2032
MinMicroViaDiameter=0
MinMicroViaDrill=0
MinHoleToHole=0.254
TrackWidth1=0.1524
TrackWidth2=0.1016
TrackWidth3=0.127
TrackWidth4=0.1524
TrackWidth5=0.254
TrackWidth6=0.508
TrackWidth7=0.762
ViaDiameter1=0.4572
ViaDrill1=0.254
ViaDiameter2=0.4064
ViaDrill2=0.2032
ViaDiameter3=0.4572
ViaDrill3=0.254
dPairWidth1=0.1524
dPairGap1=0.1524
dPairViaGap1=0.25
SilkLineWidth=0.127
SilkTextSizeV=0.762
SilkTextSizeH=0.762
SilkTextSizeThickness=0.127
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.254
CopperTextSizeV=1.524
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.03809999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.1524
OthersTextSizeV=1.016
OthersTextSizeH=1.016
OthersTextSizeThickness=0.1524
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.1016
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=TOP
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND1
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=SIGNAL_1
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=POWER_1
Type=1
Enabled=1
[pcbnew/Layer.In4.Cu]
Name=SIGNAL_2
Type=0
Enabled=1
[pcbnew/Layer.In5.Cu]
Name=GND_2
Type=1
Enabled=1
[pcbnew/Layer.In6.Cu]
Name=GND_3
Type=1
Enabled=1
[pcbnew/Layer.In7.Cu]
Name=SIGNAL_3
Type=0
Enabled=1
[pcbnew/Layer.In8.Cu]
Name=POWER_2
Type=1
Enabled=1
[pcbnew/Layer.In9.Cu]
Name=SIGNAL_4
Type=0
Enabled=1
[pcbnew/Layer.In10.Cu]
Name=GND_4
Type=1
Enabled=1
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=BOTTOM
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.4572
uViaDrill=0.254
dPairWidth=0.1524
dPairGap=0.1524
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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Sierra 12 layer Board/Twelve Layer Board.sch Normal file
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Sierra 12 layer Board/meta/Images/Design Rules.JPG Normal file
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Sierra 12 layer Board/meta/Images/Net Classes.JPG Normal file
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Sierra 12 layer Board/meta/Images/Solder Mask & Paste.JPG Normal file
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Sierra 12 layer Board/meta/Images/Text & Graphics.JPG Normal file
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Sierra 12 layer Board/meta/Images/Thumbs.db Normal file
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Sierra 12 layer Board/meta/Images/Trace & Vias.JPG Normal file
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Sierra 12 layer Board/meta/Images/layout.jpg Normal file
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Sierra 12 layer Board/meta/Images/schematic.jpg Normal file
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Sierra 12 layer Board/meta/Thumbs.db Normal file
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Sierra 12 layer Board/meta/info.html Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
<title>Sierra Circuit 12 Layer </title>
</head>
<body>
<h2>Sierra Circuit - 12 Layer</h2>
<img src="icon.png" alt="Sierra Circuit"/>
<p> This Template consist of following
<br> 1. Schematic Template with 1 page, user can create more pages. It is ideal to keep block diagram in page1, schematic in rest of the pages. Final page should consist of revision history.
<br> 2. Default board (Layout) with Sierra Circuit rules for 12-layerboards, It consist of standard stackup, consumers can create custom stackup.
</p>
<br> For details visit us at https://www.protoexpress.com or CALL US (800) 763.7503
Template Information & Rules are as follows.
<br>
<br> Schematic Sample
<br> <img src="Images/schematic.jpg" alt="Schematic"/>
<br>
<br>
<br> Layout Sample
<br> <img src="Images/layout.jpg" alt="layout"/>
<br>
<br>
<br> Design Rules details
<br> <img src="Images/Layers.JPG" alt="Layers"/>
<br>
<br>
<br> <img src="Images/Text & Graphics.JPG" alt="Text & Graphics"/>
<br>
<br>
<br> <img src="Images/Design Rules.JPG" alt="Design Rules"/>
<br>
<br>
<br> <img src="Images/Net Classes.JPG" alt="Net Classes"/>
<br>
<br>
<br> <img src="Images/Trace & Vias.JPG" alt="Trace & Vias"/>
<br>
<br>
<br> <img src="Images/Solder Mask & Paste.JPG" alt="Solder Mask & Paste"/>
</body>
</html>

14292
Sierra 2 layer Board/Two Layer Board.kicad_pcb Normal file
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Sierra 2 layer Board/Two Layer Board.pro Normal file
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update=09/24/19 08:50:34
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.5748
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1016
MinViaDiameter=0.4064
MinViaDrill=0.2032
MinMicroViaDiameter=0
MinMicroViaDrill=0
MinHoleToHole=0.254
TrackWidth1=0.1524
TrackWidth2=0.1016
TrackWidth3=0.127
TrackWidth4=0.1524
TrackWidth5=0.254
TrackWidth6=0.508
TrackWidth7=0.762
ViaDiameter1=0.4572
ViaDrill1=0.254
ViaDiameter2=0.4064
ViaDrill2=0.2032
ViaDiameter3=0.4572
ViaDrill3=0.254
dPairWidth1=0.1524
dPairGap1=0.1524
dPairViaGap1=0.25
SilkLineWidth=0.127
SilkTextSizeV=0.762
SilkTextSizeH=0.762
SilkTextSizeThickness=0.127
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.254
CopperTextSizeV=1.524
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.03809999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.1524
OthersTextSizeV=1.016
OthersTextSizeH=1.016
OthersTextSizeThickness=0.1524
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.1016
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=TOP
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=BOTTOM
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.4572
uViaDrill=0.254
dPairWidth=0.1524
dPairGap=0.1524
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

2075
Sierra 2 layer Board/Two Layer Board.sch Normal file
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Sierra 2 layer Board/meta/info.html Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
<title>Sierra Circuit 2 Layer </title>
</head>
<body>
<h2>Sierra Circuit - 2 Layer</h2>
<img src="icon.png" alt="Sierra Circuit"/>
<p> This Template consist of following
<br> 1. Schematic Template with 1 page, user can create more pages. It is ideal to keep block diagram in page1, schematic in rest of the pages. Final page should consist of revision history.
<br> 2. Default board (Layout) with Sierra Circuit rules for 2-layerboards, It consist of standard stackup, consumers can create custom stackup.
</p>
<br> For details visit us at https://www.protoexpress.com or CALL US (800) 763.7503
Template Information & Rules are as follows.
<br>
<br> Schematic Sample
<br> <img src="Images/schematic.jpg" alt="Schematic"/>
<br>
<br>
<br> Layout Sample
<br> <img src="Images/layout.jpg" alt="layout"/>
<br>
<br>
<br> Design Rules details
<br> <img src="Images/Layers.JPG" alt="Layers"/>
<br>
<br>
<br> <img src="Images/Text & Graphics.JPG" alt="Text & Graphics"/>
<br>
<br>
<br> <img src="Images/Design Rules.JPG" alt="Design Rules"/>
<br>
<br>
<br> <img src="Images/Net Classes.JPG" alt="Net Classes"/>
<br>
<br>
<br> <img src="Images/Trace & Vias.JPG" alt="Trace & Vias"/>
<br>
<br>
<br> <img src="Images/Solder Mask & Paste.JPG" alt="Solder Mask & Paste"/>
</body>
</html>

14889
Sierra 4 layer Board/Four Layer Board.kicad_pcb Normal file
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258
Sierra 4 layer Board/Four Layer Board.pro Normal file
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update=09/24/19 08:52:50
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=4
BoardThickness=1.5748
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1016
MinViaDiameter=0.4064
MinViaDrill=0.2032
MinMicroViaDiameter=0
MinMicroViaDrill=0
MinHoleToHole=0.254
TrackWidth1=0.1524
TrackWidth2=0.1016
TrackWidth3=0.127
TrackWidth4=0.1524
TrackWidth5=0.254
TrackWidth6=0.508
TrackWidth7=0.762
ViaDiameter1=0.4572
ViaDrill1=0.254
ViaDiameter2=0.4064
ViaDrill2=0.2032
ViaDiameter3=0.4572
ViaDrill3=0.254
dPairWidth1=0.1524
dPairGap1=0.1524
dPairViaGap1=0.25
SilkLineWidth=0.127
SilkTextSizeV=0.762
SilkTextSizeH=0.762
SilkTextSizeThickness=0.127
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.254
CopperTextSizeV=1.524
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.03809999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.1524
OthersTextSizeV=1.016
OthersTextSizeH=1.016
OthersTextSizeThickness=0.1524
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.1016
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=TOP
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=POWER
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=BOTTOM
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.4572
uViaDrill=0.254
dPairWidth=0.1524
dPairGap=0.1524
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

2164
Sierra 4 layer Board/Four Layer Board.sch Normal file
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Sierra 4 layer Board/meta/Images/Design Rules.JPG Normal file
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Sierra 4 layer Board/meta/Images/Solder Mask & Paste.JPG Normal file
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Sierra 4 layer Board/meta/Images/Text & Graphics.JPG Normal file
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Sierra 4 layer Board/meta/Images/Thumbs.db Normal file
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Sierra 4 layer Board/meta/Images/Trace & Vias.JPG Normal file
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Sierra 4 layer Board/meta/Thumbs.db Normal file
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47
Sierra 4 layer Board/meta/info.html Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
<title>Sierra Circuit 4 Layer </title>
</head>
<body>
<h2>Sierra Circuit - 4 Layer</h2>
<img src="icon.png" alt="Sierra Circuit"/>
<p> This Template consist of following
<br> 1. Schematic Template with 1 page, user can create more pages. It is ideal to keep block diagram in page1, schematic in rest of the pages. Final page should consist of revision history.
<br> 2. Default board (Layout) with Sierra Circuit rules for 4-layerboards, It consist of standard stackup, consumers can create custom stackup.
</p>
<br> For details visit us at https://www.protoexpress.com or CALL US (800) 763.7503
Template Information & Rules are as follows.
<br>
<br> Schematic Sample
<br> <img src="Images/schematic.jpg" alt="Schematic"/>
<br>
<br>
<br> Layout Sample
<br> <img src="Images/layout.jpg" alt="layout"/>
<br>
<br>
<br> Design Rules details
<br> <img src="Images/Layers.JPG" alt="Layers"/>
<br>
<br>
<br> <img src="Images/Text & Graphics.JPG" alt="Text & Graphics"/>
<br>
<br>
<br> <img src="Images/Design Rules.JPG" alt="Design Rules"/>
<br>
<br>
<br> <img src="Images/Net Classes.JPG" alt="Net Classes"/>
<br>
<br>
<br> <img src="Images/Trace & Vias.JPG" alt="Trace & Vias"/>
<br>
<br>
<br> <img src="Images/Solder Mask & Paste.JPG" alt="Solder Mask & Paste"/>
</body>
</html>

15679
Sierra 6 layer Board/Six Layer Board.kicad_pcb Normal file
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258
Sierra 6 layer Board/Six Layer Board.pro Normal file
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update=09/24/19 08:54:58
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=6
BoardThickness=1.5748
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1016
MinViaDiameter=0.4064
MinViaDrill=0.2032
MinMicroViaDiameter=0
MinMicroViaDrill=0
MinHoleToHole=0.254
TrackWidth1=0.1524
TrackWidth2=0.1016
TrackWidth3=0.127
TrackWidth4=0.1524
TrackWidth5=0.254
TrackWidth6=0.508
TrackWidth7=0.762
ViaDiameter1=0.4572
ViaDrill1=0.254
ViaDiameter2=0.4064
ViaDrill2=0.2032
ViaDiameter3=0.4572
ViaDrill3=0.254
dPairWidth1=0.1524
dPairGap1=0.1524
dPairViaGap1=0.25
SilkLineWidth=0.127
SilkTextSizeV=0.762
SilkTextSizeH=0.762
SilkTextSizeThickness=0.127
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.254
CopperTextSizeV=1.524
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.03809999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.1524
OthersTextSizeV=1.016
OthersTextSizeH=1.016
OthersTextSizeThickness=0.1524
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.1016
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=TOP
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=SIGNAL_1
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=SIGNAL_2
Type=0
Enabled=1
[pcbnew/Layer.In4.Cu]
Name=POWER
Type=1
Enabled=1
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=BOTTOM
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.4572
uViaDrill=0.254
dPairWidth=0.1524
dPairGap=0.1524
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

2231
Sierra 6 layer Board/Six Layer Board.sch Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
<title>Sierra Circuit 6 Layer </title>
</head>
<body>
<h2>Sierra Circuit - 6 Layer</h2>
<img src="icon.png" alt="Sierra Circuit">
<p> This Template consist of following
<br> 1. Schematic Template with 1 page, user can create more pages. It is ideal to keep block diagram in page1, schematic in rest of the pages. Final page should consist of revision history.
<br> 2. Default board (Layout) with Sierra Circuit rules for 6-layerboards, It consist of standard stackup, consumers can create custom stackup.
</p>
<br> For details visit us at https://www.protoexpress.com or CALL US (800) 763.7503
Template Information & Rules are as follows.
<br>
<br> Schematic Sample
<br> <img src="Images/schematic.jpg" alt="Schematic"/>
<br>
<br>
<br> Layout Sample
<br> <img src="Images/layout.jpg" alt="layout"/>
<br>
<br>
<br> Design Rules details
<br> <img src="Images/Layers.JPG" alt="Layers"/>
<br>
<br>
<br> <img src="Images/Text & Graphics.JPG" alt="Text & Graphics"/>
<br>
<br>
<br> <img src="Images/Design Rules.JPG" alt="Design Rules"/>
<br>
<br>
<br> <img src="Images/Net Classes.JPG" alt="Net Classes"/>
<br>
<br>
<br> <img src="Images/Trace & Vias.JPG" alt="Trace & Vias"/>
<br>
<br>
<br> <img src="Images/Solder Mask & Paste.JPG" alt="Solder Mask & Paste"/>
</body>
</html>

15263
Sierra 8 layer Board/Eight Layer Board.kicad_pcb Normal file
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258
Sierra 8 layer Board/Eight Layer Board.pro Normal file
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update=09/24/19 08:56:40
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=8
BoardThickness=1.5748
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1016
MinViaDiameter=0.4064
MinViaDrill=0.2032
MinMicroViaDiameter=0
MinMicroViaDrill=0
MinHoleToHole=0.254
TrackWidth1=0.1524
TrackWidth2=0.1016
TrackWidth3=0.127
TrackWidth4=0.1524
TrackWidth5=0.254
TrackWidth6=0.508
TrackWidth7=0.762
ViaDiameter1=0.4572
ViaDrill1=0.254
ViaDiameter2=0.4064
ViaDrill2=0.2032
ViaDiameter3=0.4572
ViaDrill3=0.254
dPairWidth1=0.1524
dPairGap1=0.1524
dPairViaGap1=0.25
SilkLineWidth=0.127
SilkTextSizeV=0.762
SilkTextSizeH=0.762
SilkTextSizeThickness=0.127
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.254
CopperTextSizeV=1.524
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.03809999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.1524
OthersTextSizeV=1.016
OthersTextSizeH=1.016
OthersTextSizeThickness=0.1524
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.1016
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=TOP
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND_1
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=SIGNAL_1
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=POWER_1
Type=1
Enabled=1
[pcbnew/Layer.In4.Cu]
Name=POWER_2
Type=1
Enabled=1
[pcbnew/Layer.In5.Cu]
Name=SIGNAL_2
Type=0
Enabled=1
[pcbnew/Layer.In6.Cu]
Name=GND_2
Type=1
Enabled=1
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=BOTTOM
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.4572
ViaDrill=0.254
uViaDiameter=0.4572
uViaDrill=0.254
dPairWidth=0.1524
dPairGap=0.1524
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

2242
Sierra 8 layer Board/Eight Layer Board.sch Normal file
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Sierra 8 layer Board/meta/info.html Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
<title>Sierra Circuit 8 Layer </title>
</head>
<body>
<h2>Sierra Circuit - 8 Layer</h2>
<img src="icon.png" alt="Sierra Circuit"/>
<p> This Template consist of following
<br> 1. Schematic Template with 1 page, user can create more pages. It is ideal to keep block diagram in page1, schematic in rest of the pages. Final page should consist of revision history.
<br> 2. Default board (Layout) with Sierra Circuit rules for 8-layerboards, It consist of standard stackup, consumers can create custom stackup.
</p>
<br> For details visit us at https://www.protoexpress.com or CALL US (800) 763.7503
Template Information & Rules are as follows.
<br>
<br> Schematic Sample
<br> <img src="Images/schematic.jpg" alt="Schematic"/>
<br>
<br>
<br> Layout Sample
<br> <img src="Images/layout.jpg" alt="layout"/>
<br>
<br>
<br> Design Rules details
<br> <img src="Images/Layers.JPG" alt="Layers"/>
<br>
<br>
<br> <img src="Images/Text & Graphics.JPG" alt="Text & Graphics"/>
<br>
<br>
<br> <img src="Images/Design Rules.JPG" alt="Design Rules"/>
<br>
<br>
<br> <img src="Images/Net Classes.JPG" alt="Net Classes"/>
<br>
<br>
<br> <img src="Images/Trace & Vias.JPG" alt="Trace & Vias"/>
<br>
<br>
<br> <img src="Images/Solder Mask & Paste.JPG" alt="Solder Mask & Paste"/>
</body>
</html>